Microprocessors generally include one or more arithmetic logic units (ALUs) in the execution pipeline to perform arithmetic and logical operations. ALUs may be characterized by the number of input operands and/or the number of mathematical and logical operations that they support. Some combinations of mathematical operations occur sufficiently often to justify the inclusion of a customized data path in an ALU to accommodate a specific operation. For example, an ALU may accommodate a fused multiply-add (FMA) operation in which the product of two floating point values is added to an accumulated floating point value using a single operation and rounding. Determining whether to implement a specific mathematical operation in a special purpose or complex ALU involves a cost/performance tradeoff. A factor that may influence any such determination is the extent to which a complex ALU may be utilized to perform simpler operations at times when no pending operation requires the full functionality of the complex ALU and/or or the extent to which an underutilized ALU may be employed to improve reliability via redundant execution of less complex instructions.